languages/verilog: init module

This commit is contained in:
AleksandarZhekovski 2025-10-04 00:25:35 +03:00
commit 567de2c259
4 changed files with 67 additions and 0 deletions

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@ -86,6 +86,7 @@ isMaximal: {
haskell.enable = false;
ruby.enable = false;
fsharp.enable = false;
verilog.enable = false;
tailwind.enable = false;
svelte.enable = false;