diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml
index 3f786d8..fff5aea 100644
--- a/.github/workflows/rust.yml
+++ b/.github/workflows/rust.yml
@@ -39,6 +39,9 @@ jobs:
             toolchain: nightly
             components: rust-src
             build_std: true
+          # sparc64 uses experimental asm features
+          - target: sparc64-unknown-linux-gnu
+            toolchain: nightly
 
     steps:
     - name: "Checkout"
diff --git a/crates/asm/src/lib.rs b/crates/asm/src/lib.rs
index 01afbde..c877c1a 100644
--- a/crates/asm/src/lib.rs
+++ b/crates/asm/src/lib.rs
@@ -6,10 +6,13 @@
 //! faster?
 //!
 //! Supports `x86_64`, `aarch64`, `riscv64`, `loongarch64`, `s390x`,
-//! `powerpc64`, `arm` (armv7), and `riscv32` architectures.
+//! `powerpc64`, `arm` (armv7), `riscv32`, and `sparc64` architectures.
 
 #![no_std]
-#![cfg_attr(target_arch = "powerpc64", feature(asm_experimental_arch))]
+#![cfg_attr(
+  any(target_arch = "powerpc64", target_arch = "sparc64"),
+  feature(asm_experimental_arch)
+)]
 
 // Ensure we're compiling for a supported architecture.
 #[cfg(not(any(
@@ -20,11 +23,12 @@
   target_arch = "s390x",
   target_arch = "powerpc64",
   target_arch = "arm",
-  target_arch = "riscv32"
+  target_arch = "riscv32",
+  target_arch = "sparc64"
 )))]
 compile_error!(
   "Unsupported architecture: only x86_64, aarch64, riscv64, loongarch64, \
-   s390x, powerpc64, arm, and riscv32 are supported"
+   s390x, powerpc64, arm, riscv32, and sparc64 are supported"
 );
 
 // Per-arch syscall implementations live in their own module files.
@@ -52,6 +56,9 @@ mod arch;
 #[cfg(target_arch = "riscv32")]
 #[path = "riscv32.rs"]
 mod arch;
+#[cfg(target_arch = "sparc64")]
+#[path = "sparc64.rs"]
+mod arch;
 
 /// Copies `n` bytes from `src` to `dest`.
 ///
diff --git a/crates/asm/src/sparc64.rs b/crates/asm/src/sparc64.rs
new file mode 100644
index 0000000..020657e
--- /dev/null
+++ b/crates/asm/src/sparc64.rs
@@ -0,0 +1,179 @@
+//! Syscall implementations for `sparc64`.
+
+use super::{StatfsBuf, SysInfo, UtsNameBuf};
+
+pub(super) unsafe fn sys_open(path: *const u8, flags: i32) -> i32 {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 5i64,  // SYS_open
+      inlateout("o0") path => ret,
+      in("o1") flags,
+      in("o2") 0i32,  // mode
+      options(nostack)
+    );
+    #[allow(clippy::cast_possible_truncation)]
+    {
+      ret as i32
+    }
+  }
+}
+
+pub(super) unsafe fn sys_read(fd: i32, buf: *mut u8, count: usize) -> isize {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 3i64,  // SYS_read
+      inlateout("o0") fd as i64 => ret,
+      in("o1") buf,
+      in("o2") count,
+      options(nostack)
+    );
+    ret as isize
+  }
+}
+
+pub(super) unsafe fn sys_write(fd: i32, buf: *const u8, count: usize) -> isize {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 4i64,  // SYS_write
+      inlateout("o0") fd as i64 => ret,
+      in("o1") buf,
+      in("o2") count,
+      options(nostack)
+    );
+    ret as isize
+  }
+}
+
+pub(super) unsafe fn sys_close(fd: i32) -> i32 {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 6i64,  // SYS_close
+      inlateout("o0") fd as i64 => ret,
+      options(nostack)
+    );
+    #[allow(clippy::cast_possible_truncation)]
+    {
+      ret as i32
+    }
+  }
+}
+
+pub(super) unsafe fn sys_uname(buf: *mut UtsNameBuf) -> i32 {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 189i64,  // SYS_newuname
+      inlateout("o0") buf => ret,
+      options(nostack)
+    );
+    #[allow(clippy::cast_possible_truncation)]
+    {
+      ret as i32
+    }
+  }
+}
+
+pub(super) unsafe fn sys_statfs(path: *const u8, buf: *mut StatfsBuf) -> i32 {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 157i64,  // SYS_statfs
+      inlateout("o0") path => ret,
+      in("o1") buf,
+      options(nostack)
+    );
+    #[allow(clippy::cast_possible_truncation)]
+    {
+      ret as i32
+    }
+  }
+}
+
+pub(super) unsafe fn sys_sysinfo(info: *mut SysInfo) -> i64 {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 214_i64, // __NR_sysinfo
+      inlateout("o0") info => ret,
+      options(nostack)
+    );
+    ret
+  }
+}
+
+pub(super) unsafe fn sys_sched_getaffinity(
+  pid: i32,
+  mask_size: usize,
+  mask: *mut u8,
+) -> i32 {
+  unsafe {
+    let ret: i64;
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      "bcs,a %xcc, 1f",
+      "sub %g0, %o0, %o0",
+      "1:",
+      nr = in(reg) 260i64,  // __NR_sched_getaffinity
+      inlateout("o0") pid as i64 => ret,
+      in("o1") mask_size,
+      in("o2") mask,
+      options(nostack)
+    );
+    #[allow(clippy::cast_possible_truncation)]
+    {
+      ret as i32
+    }
+  }
+}
+
+pub(super) unsafe fn sys_exit(code: i32) -> ! {
+  unsafe {
+    core::arch::asm!(
+      "mov {nr}, %g1",
+      "t 0x6d",
+      nr = in(reg) 1i64,  // SYS_exit
+      in("o0") code,
+      options(noreturn, nostack)
+    );
+  }
+}
diff --git a/crates/lib/src/cpu.rs b/crates/lib/src/cpu.rs
index 2b10a32..3bb53a0 100644
--- a/crates/lib/src/cpu.rs
+++ b/crates/lib/src/cpu.rs
@@ -207,6 +207,32 @@ fn get_cpu_freq_mhz() -> Option<u32> {
       }
     }
   }
+  // SPARC exposes its clock as `Cpu0ClkTck : <hex>`,
+  // which signifies ticks per second in hex.
+  if let Some(val) = extract_field(data, b"Cpu0ClkTck") {
+    let mut hz = 0u64;
+    let mut seen = false;
+    for &b in val.as_bytes() {
+      let d = match b {
+        b'0'..=b'9' => Some(u64::from(b - b'0')),
+        b'a'..=b'f' => Some(u64::from(b - b'a' + 10)),
+        b'A'..=b'F' => Some(u64::from(b - b'A' + 10)),
+        _ => None,
+      };
+      match d {
+        Some(d) => {
+          hz = hz * 16 + d;
+          seen = true;
+        },
+        None if seen => break,
+        None => {},
+      }
+    }
+    if hz > 0 {
+      #[allow(clippy::cast_possible_truncation)]
+      return Some((hz / 1_000_000) as u32);
+    }
+  }
   None
 }
 
diff --git a/microfetch/src/main.rs b/microfetch/src/main.rs
index 68a7bbf..42bad34 100644
--- a/microfetch/src/main.rs
+++ b/microfetch/src/main.rs
@@ -1,6 +1,9 @@
 #![no_std]
 #![no_main]
-#![cfg_attr(target_arch = "powerpc64", feature(asm_experimental_arch))]
+#![cfg_attr(
+  any(target_arch = "powerpc64", target_arch = "sparc64"),
+  feature(asm_experimental_arch)
+)]
 
 extern crate alloc;
 
@@ -168,6 +171,28 @@ unsafe extern "C" fn _start() {
   );
 }
 
+#[cfg(target_arch = "sparc64")]
+#[unsafe(no_mangle)]
+#[unsafe(naked)]
+unsafe extern "C" fn _start() {
+  naked_asm!(
+    // SPARC v9: kernel sets %sp biased by -2047; argc is at
+    // %sp + 2047 + 128 (bias + 128-byte register save area).
+    // See glibc sysdeps/sparc/sparc64/start.S.
+    "mov %g0, %fp",
+    "add %sp, 2047+128, %o0",  // first arg = &argc
+    "add %sp, 2047, %sp",      // unbias
+    "sub %sp, 176, %sp",       // reserve register save area
+    "and %sp, -16, %sp",       // align
+    "sub %sp, 2047, %sp",      // rebias
+    "call {entry_rust}",
+    "nop",                     // delay slot
+    "mov 1, %g1",              // SYS_exit
+    "t 0x6d",
+    entry_rust = sym entry_rust,
+  );
+}
+
 // Global allocator
 #[global_allocator]
 static ALLOCATOR: BumpAllocator = BumpAllocator::new();