dev: Added config bits and copy of periph init code

This commit is contained in:
A.M. Rowsell 2025-07-31 16:33:38 -04:00
commit 25c351be04
Signed by untrusted user who does not match committer: amr
GPG key ID: E0879EDBDB0CA7B1

102
main.cpp
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@ -6,9 +6,111 @@
// file, You can obtain one at http://mozilla.org/MPL/2.0/. // file, You can obtain one at http://mozilla.org/MPL/2.0/.
// This Source Code Form is "Incompatible With Secondary Licenses", as // This Source Code Form is "Incompatible With Secondary Licenses", as
// defined by the Mozilla Public License, v. 2.0. // defined by the Mozilla Public License, v. 2.0.
// PIC32MX270F256B Configuration Bit Settings
// 'C' source line config statements
// DEVCFG3
#pragma config USERID = 0xBEEF // Enter Hexadecimal value (Enter Hexadecimal value)
#pragma config PMDL1WAY = OFF // Peripheral Module Disable Configuration (Allow multiple reconfigurations)
#pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow multiple reconfigurations)
#pragma config FUSBIDIO = ON // USB USID Selection (Controlled by the USB Module)
#pragma config FVBUSONIO = ON // USB VBUS ON Selection (Controlled by USB Module)
// DEVCFG2
#pragma config FPLLIDIV = DIV_2 // PLL Input Divider (2x Divider)
#pragma config FPLLMUL = MUL_24 // PLL Multiplier (24x Multiplier)
#pragma config UPLLIDIV = DIV_2 // USB PLL Input Divider (2x Divider)
#pragma config UPLLEN = ON // USB PLL Enable (Enabled)
#pragma config FPLLODIV = DIV_8 // System PLL Output Clock Divider (PLL Divide by 8)
// DEVCFG1
#pragma config FNOSC = FRCPLL // Oscillator Selection Bits (Fast RC Osc with PLL)
#pragma config FSOSCEN = ON // Secondary Oscillator Enable (Enabled)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = OFF // Primary Oscillator Configuration (Primary osc disabled)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_2 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/2)
#pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable (Watchdog Timer is in Non-Window Mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window Size is 25%)
// DEVCFG0
#pragma config JTAGEN = ON // JTAG Enable (JTAG Port Enabled)
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC2/PGED2)
#pragma config PWP = OFF // Program Flash Write Protect (Disable)
#pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF // Code Protect (Protection Disabled)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include <xc.h> #include <xc.h>
void sendChar(uint8_t c) {
U1TXREG = c;
while(!U1STAbits.TRMT); // wait for transmission
return;
}
uint8_t appInfo(uint8_t *msg, uint16_t len) {
uint16_t offset = 0;
do {
sendChar(*(msg+offset));
offset++;
} while(--len);
return 0;
}
uint8_t initSystem(void) {
/* set up GPIO */
SYSKEY = 0x0;
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;
CFGCON &= ~(1<<13); // unlock PPS
SDI1R = 0b0110; // RC8
SDI2R = 0b0100; // RB2
SS2R = 0b0111; // RC4
RPB5R = 0b0011; // SD01
RPC0R = 0b0001; // U1TX
SYSKEY = 0x12345678; // lock SYSKEY
/* Set up SPI1 */
SPI1BRG = 1; // 1.5MHz
SPI1CONbits.ENHBUF = 1; // enable enhanced buffer
SPI1CONbits.MSTEN = 1; // master mode
SPI1CONbits.STXISEL = 0b10; // interrupt on half-empty or more
/* set up UART */
U1BRG = 38; // 9600 baud
U1STAbits.UTXEN = 1; // enable transmitter
U1MODEbits.ON = 1; // enable UART
/* set up DMA */
// clear all 4 DMA channel flags & IE
// IEC1CLR = 0xF0000000;
// IFS1CLR = 0xF0000000;
//
// DMACONbits.ON = 1; //enable DMA controller
//
// // Channel 0: SPI2 receive triggers DMA to buffer
// DCH0ECONbits.CHSIRQ = 51; // SPI2 receive complete
// DCH0ECONbits.SIRQEN = 1; // enable trigger
// DCH0CONbits.CHCHN = 1; // enable chaining
// DCH0CONbits.CHAEN = 1; // auto enable
// DCH0SSA = KVA_TO_PA(&SPI2BUF); // source is SPI2BUF
// DCH0DSA = KVA_TO_PA(dmaBuffer);
// DCH0SSIZ = 1;
// DCH0DSIZ = 16;
// DCH0CSIZ = 16; // copy 1 sets of 2 bytes from source to destination
//
// IEC1SET = 0x10000000; // channel 0 interrupt enable
// DCH0CONbits.CHEN = 1; // enable channel
return 0;
}
extern "C" int main(void) { extern "C" int main(void) {
while(1) { while(1) {